Sharp MZ-3500 Manual de usuario descargar pdf (Pagina 68)

MZ3500

6-6. 8253 Controls

Baud rate of this interface will be determined by the clock

output of the 8253. The 8251 is configured such that its

baud rate is 1/16 of the input clock and has the following

relation between the 8253 output clock and the baud rate:

8253 input frequency: 2457.6kHz

8253 Mode set: Mode 3(rec’angle waveform rate generator)

Baud rate

825 3

Output frequency

8253

Parameter

1 1 0 ,t -

1 7 60hz

1 3 9 6.3 6

300 4 800 5 I 2

600 9600

256

I 200

1 9200

128

24 00

384 00

4 800 76800

9 6 00

153600

1 6

Control signals

Signal name

Symbol

IN/OUT

Function

Transmission enabled

CS “* Peripheral When high, data input from a peripheral is enabled.

When low, data input from a peripheral is disabled.

Data set ready DR

-♦ Peripheral

Goes high when power is on to the interface unit.

Carrier detect

Peripheral

(SW6-ON) High at all times when power is on to the interface unit.

(SW6-OFF) Goes high only when data is on output.

Beady

READY

Peripheral

Data output from the interface is enabled.

(ON) Data is output from the interface.

(OFF) Waits for data output.

NOTE: A maximum of two bytes are output after the signal goes from high to low

state.

Equipment ready ER

•*- Peripheral

Indicates that the peripheral is ready, it results in an error if low or open when data

is sent from the interface. This signal will be invalidated when the SW5 is turned

off.

Paper out

PO Peripheral

(SW7-ON) Causes an error if set high during data output.

(SW7-OFF) Causes an error if set low during data output.

6-7. Description of LSI's

1) UPD8251AC (Programmable Communication Interface)

The UPD8251A is a USART (Universal Synchronous/

Asynchronous Receiver/Transmitter that was specifical

ly designed for data communication.

The USART receives parallel data from the CPU and

converts it into serial data before transmitting. Also,

serial data is received from an external circuit and trans

ferred to the CPU after converting it into parallel. The

CPU can monitor the current state of the USART at

any time (data transfer error, and control signal of

. SYNDET and TXEMPTY.

.-eatures

• 8080A/8085A compatible

• Synchronous/asychronous operation

• Synchronous operation

5 — 8 bits character

Clock rate: baud rate x 1, x16, x64

BREAK character generation

Stop bit; 1, 1.5, 2 bits

Error start bit detection

Automatic break detection and operation.

• Baud rate: DC — 64K baud

• Full-duplex

Double buffer type transmitter/receiver

• Error detect

Parity, overrun, framing

• Input/output TTL compatible

• N-channel MOS

• Single -r5V supply

Single phase TTL level clock

28-pin, plastic DIP

Intel 8251 A compatible

Pin configuration (Top View)

D2 04

--------

D3 O*-

RXD O—

GND O—

04-

D5 04-

04-

T)^ O-

----

10 -I

WHO—

cs o

C -D O

RD O

■►C

RXRDY

.28

,27

♦ODl

♦ODD

—OVCC

.24

-ORXC

-►ODTR

-►Orts

-ODSR

-ORESET

■4^—OCLK

-►OTXU

-►OTXEMPTY

[04lZ.„-o CTS

,16

-►O SYNDET BD

-►OTXRDY

Block diagram

D7-D0C>#-

RESETO

>OTXD

¥CTXK iJ

>otxe

X)RXRI)/

----

OK^

SYMJhl HI)

Internal data bus

75 -

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 115 116

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Sharp MZ-3500 Manual de usuario Pagina 68

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